IP design

IP blocks of high-speed interfaces:

CMOS 90 nm “Micron JSC”

• DDR2 PHY 533 Мb/s (reference frequency 266 MHz);
• DDL (resolution – 11 ps);
• USB2.0 PHY with OTG support.

Radiation hardened frequency synthesizers up to 832 MHz based on PLL:

• CMOS 65 nm GP TSMC
• CMOS 90 nm “Micron JSC”