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Memory Compilers Development

Since memory circuits have a lot of serial mainframes, such circuits can be formalized having broken them on elementary blocks: memory cells, read amplifiers, decoders, etc. Therefore it is possible to receive layout and SPICE-like format descriptions for any configuration of memory circuit on the stipulation that the library contains circuit and layout descriptions for each block, the rules of the block placement from each other and the order of their electric connection are known. It can be done with the use of specialized software.

Memory compilers are the software modules permitting to generate memory blocks with the required sizes in short terms and automatically. Then such blocks are used by customers to design ASICs.

Behind its shoulders, AlphaCHIP LLC team has long-term experience of memory compilers development. Such developments were done with and for the leaders of the world semiconductor market - Motorola, Inc. and Freescale Semiconductor, Inc.

During more than ten years, AlphaCHIP Memory Compiler Team stored knowledge and huge experience to design both memory compilers and digital blocks can be used for various purposes.


The variety of the circuits and blocks have been developed by the team covers the wide range of minimal CMOS gate lengths from 250 to 45 nm. The variety covers both the standard bulk processes and high-speed SOI processes.

The team has experience to develop memory cells for the storage of different data types: single port and dual port RAM and ROM. All the developed cells are passed through mandatory characterization with the use of test chips.


AlphaCHIP LLC is ready to render memory compiler development services. As the result, the customer will receive "ready to use" product using front-end design flow for embedded memories at SoC-level. The state of the art CAD tools of Cadence, Mentor Graphics, Synopsys are used within design stage.

When the customer defines the necessary configuration parameters of the memory circuit (number of layers, data bus lengths, architecture, existence of test and auxiliary regimes, manufacture and exploitation conditions etc.), the compiler can execute the following steps automatically:

  • development of views for both FrontEnd and BackEnd levels ((layout (GDS), netlist description, data for placement and routing at SoC level (LEF), behavioral model (Verilog, VHDL), layout verification (DRC, LVS));
  • RC-elements extraction from layout, memory characterization (simulation for speed and power parameter definition);
  • development of the all necessary views for high-level system synthesis (.lib and .db formats);
  • generation and verification of the final database includes the set of necessary views as well as documentation.

The access to the compilers is provided through user-friendly WEB-interface with the features of ASIC parameters advanced vision and eventual configuration versions. This affords the opportunity to choose the best ratio square / speed / power.

All the projects of the AlphaCHIP Memory Compiler Team have been done in accordance with Statement of Works in spite of strict requirements to projects milestones. Any project is supported professionally and timely.

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