Intellectual Property

During its history, AlphaCHIP has developed more than 140 libraries of standard cell and I/O elements, more than 250 compilers for almost all possible memory circuit architectures, more than 100 complex functional blocks as well as a number of software tools & packages for design automation. All developments were carried out in accordance with customer’s specifications and for the most modern silicon technologies and IT standards of that time. A number of project results surpassed the existing analogues in certain parameters, such as: speed, area, power consumption, resistance to extreme temperatures and radiation exposure, which required a usage of innovative IT- and design solutions. A number of results have been patented jointly with the customers. A number of the patents have been obtained in Europe, South Korea, Taiwan, Japan, China and the United States, for example:

• Method and apparatus for distortion analysis in nonlinear circuits (has been patented with ## AU2002363921A1; WO2004040509A1; US2004083437A1; US7007253B2);
• METHOD FOR SIMULATING CIRCUITS USING HARMONIC BALANCE, AND APPARATUS THEREFORE (has been patented with ## WO9936872A1; WO9936872A8);
• Fast simulation of circuitry having soi transistors (has been patented with ## AU2002356476A1; WO2004021252A1; US2004044510A1; US7127384B2);
• REFERENCE CIRCUIT (has been patented with ## CN101052933A; CN101052933B; EP1810108A1; WO2006038057A1; WO2006038057A8; JP2008516328A; US2008048634A1; US7710096B2);
• Circuit for electrostatic discharge protection (has been patented with ## AU2002315976A1; WO03081742A1; US2005231878A1; US7154719B2);
• Electrostatic discharge protection circuitry and method of operation (has been patented with ## CN1628385A; CN100355072C; EP1527481A2; JP2005536046A; JP4322806B2; KR20050026915A; KR101006825B1; TW200418164A; TWI282161B; WO2004015776A2; WO2004015776A3; US2004027742A1; US6724603B2).

A recently developed, but not yet patented know-how in the areas of information and semiconductor technologies includes:

• methods for memory compiler developments and related software package for supporting the development of memory compilers aimed to achievement of a specified parametric coefficient of the yield, that significantly reduces the time and improves the quality of development;
• "silicon verification" in the form of universal and flexible test chip architecture with a standardized interface, which provides significant test chips development time reduction, repeatedly usage of auxiliary test equipment, automation of a measurement of many parameters as well as significant reduction of test software development time.