Developed products and solutions

AlphaCHIP programmers and engineers have completed a number of projects to develop unique EDA tools, the analogues of which were not represented on the world market or were significantly worse in a number of consumer characteristics:

• Tool for determination of poles and zeros for digital filters simulation;
• Tool allowing usage of Inverse Laplace Transform for dynamic systems analysis (new approach is applied with the direct inclusion of blocks of subsystems described by Laplace in the analysis of transient processes);
• Harmonic analysis tool (new approach and a set of numerical procedures based on Krylov subspace techniques for harmonic balance analysis);
• Stability analysis tool for analog circuits;
• Tool for non-stationary interference simulation (a new numerical method for simulation of the non-stationary interference in electronic circuits when an arbitrary large signal is excited);
• Tool for automation of standard cell libraries development;
• Fast circuit simulation tool (10x acceleration of simulation with 90% accuracy compared to its analogous);
• Optimization package for large combinational circuits;
• Circuit resynthesis tool that reduces power consumption by 15-50%;
• Tool for automatic change of element sizes in combination circuits with optimization of power and area with maintaining the performance of the prototype, etc.

In addition, the company has developed IT solutions in the field of CAD that have no analogues:

• A set of tools and libraries of parameterized blocks for development of circuits based on the Residue Numerical System (RNS), which have a massive internal parallelism and an ability to fault tolerance simulation;
• Tool for resynthesis of combinational parts of digital circuits in order to reduce their sensitivity to interference and failures, which provides significant increase (about 20-60%) of the stability of circuits to errors,

as well as exceed foreign analogues in their characteristics:

• Tool for automatic generation of functional ECO-patches (ECO-Engineering Change Order), which allows elimination of design errors detected at the later stages of the circuit design;
• Tool for definition of equivalent errors in circuits, which allows reducing the dimensions of test sequences for verification of combinational and sequential circuits;
• Static Time Analysis tool, which implements the main features of PrimeTime (SYNOPSYS, Inc.), but surpasses it in speed and easiness of integration into the accompanying design flows;
• Hardware Accelerated Fault Simulation Engine. It is used to quantify the effectiveness of the functional patterns and estimate fault coverage. The engine is implemented in a highly parallel fashion and can be launched using graphic accelerators (GPU), which can provide 5-10 speed-up compared to standard commercial tools.